Today, Google and Qualcomm announced an extension of their partnership to bring RISC-V-based systems-on-chips (SoCs) to market with support for Wear OS, a version of Android for smartwatches and ...
Infineon’s OktoberTech in Silicon Valley provided a glimpse of the shift in power architecture with hot-swap controllers, ...
It has taken eight years and $303 million in seed and three rounds of venture funding, but NextSilicon is today delivering ...
A job listing posted to Apple's website this week reveals the company is researching RISC-V instruction set architecture solutions, suggesting future in-house chip designs might implement the ...
“To ensure secure and trustworthy execution of applications, vendors frequently embed trusted execution environments into their systems. Here, applications are protected from adversaries, including a ...
SiFive Inc., a computer chip startup that’s developing processor technology based on the open-source RISC-V instruction set architecture, said today it has raised a hefty $175 million in a late-stage ...
I was discussing with a colleague about the concept of architecture license in RISC-V. I realized that, in the open-source world, it can be a little tricky to grasp. In a traditional processor IP ...
SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Yunsup Lee, CTO of SiFive, and Dr. Krste ...
Zurich – Feb. 23, 2021 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA ...
Recently, someone who is relatively new to Hyper-V e-mailed me to ask two thought-provoking questions. The first was whether or not it is true that Hyper-V virtual machines (VMs) have direct hardware ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback